The present invention relates to multiply-and-accumulate (MAC) units including operations in carry-save adder (CSA) data format which is referred below as CSA-MAC. Furthermore, the present invention relates to the application of CSA-MAC units to feedback loop equalizers such as for instance Tomlinson-Harashima precoders.
MAC units are well known in the art. Conventional MAC units have three inputs, namely two multiplicands and one summand, each of which is in a binary form, such as a little endian format. The MAC operation includes a multiplication of the two multiplicands and an adding operation of the resulting product and the summand. The output of the MAC operation conventionally is in a binary or CSA format. The carry-save adder format is a number format where a sum and a carry portion is separately provided wherein a final operation to combine the sum portion and the carry portion to a standard binary format such as a little endian format is omitted. Because the CSA format avoids the carry rippling, it belongs to one of the fastest data formats for summation operations.
In general, MAC operations are the most basic operation type in every digital computing device so that there are many approaches to speed up the MAC operation. For instance, if such a MAC unit is employed in a loop, the overall cycle time is essentially affected by the propagation delays of its suboperations such as the multiplication and addition. As MAC units are often used in feedback loops in the digital implementation of high speed 10 equalizers such as decision feedback equalizers in receiving interfaces, Tomlinson-Harashima precoder devices in transmitting interfaces, IIR filters and the like, speeding up the MAC operation can generally lead to higher bandwidths in signal transmission.
Document U.S. Pat. No. 8,275,822 B2 discloses a digital signal processor with a multiplication engine including a first partial product generation circuit to generate a first set of unequally weighted partial products from a set of input operands; a second partial product generation circuit to generate a second set of equally weighted partial products from the set of input operands; a multiplexer to select the first set of unequally weighted partial products or the second set of equally weighted partial products in accordance with first and second multiplier modes, respectively; and a carry-save adder array configured to add the selected set of partial products, wherein, in the first multiplier mode, the carry-save adder array folds over higher-order bits of the first set of unequally weighted partial products into lower-order slots in the carry-save adder array, thereby allowing the same carry-save adder array to be used in either the first or the second multiplier modes.
Document U.S. Pat. No. 8,090,013 B2 discloses a Tomlinson-Harashima precoder with the number of stages, each stage including a multiplier, an adder, a register and a modulo operator which are subsequently coupled so that the outputs of the modulo operators are coupled with an input of the adder of the next stage. The outputs of the adders are connected with the modulo operator, and the output of the last modulo operators in the line of stage is fed back to the inputs of each of the multipliers.